Tan S, Miao Y, Palm M, Rodrigues J, Andreani P (2015)
Publication Type: Conference contribution
Publication year: 2015
Publisher: Institute of Electrical and Electronics Engineers Inc.
Conference Proceedings Title: 2015 Nordic Circuits and Systems Conference, NORCAS 2015: NORCHIP and International Symposium on System-on-Chip, SoC 2015
Event location: Oslo, NOR
ISBN: 9781467365765
DOI: 10.1109/NORCHIP.2015.7364377
This work presents a digital calibration technique in continuous-time (CT) ΔΣ analog to digital (A/D) converters. The converter is clocked at 144MHz with a low oversampling ratio (OSR) of only 8. Dynamic element matching (DEM) is not efficient to linearize the digital to analog converter (DAC) when the OSR is very low. Therefore, non-idealities in the outermost multi-bit feedback DAC are measured and then removed in the background by a digital circuit. A third-order, four-bit feedback, single-loop CT ΔΣ converter with digital background calibration circuit has been designed, simulated and implemented in 65nm CMOS process. The maximum simulated signal-to-noise and distortion ratio (SNDR) is 67.1dB within 9MHz bandwidth.
APA:
Tan, S., Miao, Y., Palm, M., Rodrigues, J., & Andreani, P. (2015). Digital background calibration in continuous-time delta-sigma analog to digital converters. In Tor Sverre Lande, Jim Torresen, Oyvind Kallevik Grutle, Ivan Ring Nielsen, Snorre Aunet (Eds.), 2015 Nordic Circuits and Systems Conference, NORCAS 2015: NORCHIP and International Symposium on System-on-Chip, SoC 2015. Oslo, NOR: Institute of Electrical and Electronics Engineers Inc..
MLA:
Tan, Siyu, et al. "Digital background calibration in continuous-time delta-sigma analog to digital converters." Proceedings of the 1st IEEE Nordic Circuits and Systems Conference, NORCAS 2015, Oslo, NOR Ed. Tor Sverre Lande, Jim Torresen, Oyvind Kallevik Grutle, Ivan Ring Nielsen, Snorre Aunet, Institute of Electrical and Electronics Engineers Inc., 2015.
BibTeX: Download