Ultra low energy and area efficient charge pump with automatic clock controller in 65 nm CMOS
Mohammadi B, Rodrigues J (2016)
Publication Type: Conference contribution
Publication year: 2016
Publisher: Institute of Electrical and Electronics Engineers Inc.
Conference Proceedings Title: 2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings
Event location: Xiamen, Fujian, CHN
ISBN: 9781467371919
DOI: 10.1109/ASSCC.2015.7387491
Abstract
A low power CMOS charge pump (CP) is proposed utilizing a new combination of charge transferring switches for a faster start-up, higher efficiency and lower reverse charge sharing. A low cost feedback mechanism observes the output voltage level and automatically switches off the clock after passing a threshold, which reduces energy dissipation by 62%. It is shown that by using one capacitor per stage, the proposed architecture reaches higher voltages compared to the competitive architectures when driving capacitive loads. The design is manufactured in a 65 nm technology, and measurement results confirm a 120% higher voltage compared to the conventional Dickson CP at 400 mV with identical area cost. The measured minimum operating voltage and highest charge pumping efficiency are 290 mV and 86%, respectively.
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Sweden (SE)How to cite
APA:
Mohammadi, B., & Rodrigues, J. (2016). Ultra low energy and area efficient charge pump with automatic clock controller in 65 nm CMOS. In 2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings. Xiamen, Fujian, CHN: Institute of Electrical and Electronics Engineers Inc..
MLA:
Mohammadi, Babak, and Joachim Rodrigues. "Ultra low energy and area efficient charge pump with automatic clock controller in 65 nm CMOS." Proceedings of the 11th IEEE Asian Solid-State Circuits Conference, A-SSCC 2015, Xiamen, Fujian, CHN Institute of Electrical and Electronics Engineers Inc., 2016.
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