A 60pJ/b 300Mb/s 128×8 Massive MIMO precoder-detector in 28nm FD-SOI

Prabhu H, Rodrigues JN, Liu L, Edfors O (2017)


Publication Type: Conference contribution

Publication year: 2017

Journal

Publisher: Institute of Electrical and Electronics Engineers Inc.

Book Volume: 60

Pages Range: 60-61

Conference Proceedings Title: Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Event location: San Francisco, CA, USA

ISBN: 9781509037575

DOI: 10.1109/ISSCC.2017.7870260

Abstract

Further exploitation of the spatial domain, as in Massive MIMO (MaMi) systems, is imperative to meet future communication requirements [1]. Up-scaling of conventional 4×4 small-scale MIMO implementations to MaMi is prohibitive in-terms of flexibility, as well as area and power cost. This work discloses a 1.1mm2 128×8 MaMi baseband chip, achieving up to 12dB array and 2× spatial multiplexing gains. The area cost compared to previous state-of-the-art MIMO implementations [2-3], is reduced by 53% and 17% for up- and down-link, respectively. Algorithm optimizations and a highly flexible framework were evaluated on real measured channels. Extensive hardware time multiplexing lowered area cost, and leveraging on flexible FD-SOI body bias and clock gating resulted in an energy efficiency of 6.56nJ/QRD and 60pJ/b at 300Mb/s detection rate.

Involved external institutions

How to cite

APA:

Prabhu, H., Rodrigues, J.N., Liu, L., & Edfors, O. (2017). A 60pJ/b 300Mb/s 128×8 Massive MIMO precoder-detector in 28nm FD-SOI. In Laura C. Fujino (Eds.), Digest of Technical Papers - IEEE International Solid-State Circuits Conference (pp. 60-61). San Francisco, CA, USA: Institute of Electrical and Electronics Engineers Inc..

MLA:

Prabhu, Hemanth, et al. "A 60pJ/b 300Mb/s 128×8 Massive MIMO precoder-detector in 28nm FD-SOI." Proceedings of the 64th IEEE International Solid-State Circuits Conference, ISSCC 2017, San Francisco, CA, USA Ed. Laura C. Fujino, Institute of Electrical and Electronics Engineers Inc., 2017. 60-61.

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