FeMFET-based High Performance, Ultra-Low Power Memory Cells for Reliable State Retention of Dataflow Networks

Darne B, Karim A, Matrangolo PA, Falk J, O'Connor I, Marchand C, Bosio A, Teich J (2025)

Publication Language: English

Publication Type: Conference contribution, Conference Contribution

Publication year: 2025

Pages Range: 1-8

Event location: Barcelona, Spain ES

Abstract

High throughput data and signal processing applications can be specified preferably by dataflow networks, which naturally enable the exploitation of parallelism both globally (at the network level) and locally (at the actor level), such as mapping each actor onto a dedicated hardware circuit. While some system-level design methodologies exist to synthesize a given network directly into hardware for maximum processing speeds, embedded systems - particularly within the IoT domain - face additional challenges, not covered by existing approaches: they must ensure reliable operation despite intermittent power supply and operate with ultra-low power constraints. Indeed, a key limitation of existing approaches is the significant latency overhead incurred when backing up internal states - thus severely impacting processing speed.

In this paper, we address these challenges by integrating circuit devices that support both volatile and non-volatile operation at a fine-grain level, enabling the concurrent and local retention of internal states. By modeling and characterizing emerging ferroelectric FeMFET technology, we merge the system-level dataflow paradigm - based on self-scheduled activations of computations - with emerging CMOS-compatible FeMFET technology for the design of actor networks.

After introducing the dataflow concept and presenting the fundamentals of ferroelectric devices and logic devices, we present a Non-Volatile (NV) ferroelectric backup latch. Then, we present the circuitry to extend a single-bit scan Flip-Flop (FF) by this NV-Latch and a protocol to backup each FF into such an NV-Latch upon reception of a shutdown signal and restoration of the FF state when given a wakeup signal. Finally, this hybrid memory cell is integrated into the design of actors for state retention and compared against a scan-chain-based retention technique in terms of power and latency savings, achieving up to 47% power savings.

Authors with CRIS profile

Abrarul Karim Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Joachim Falk Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Related research project(s)

Automatic Cross-Layer Synthesis of High Performance, (Ultra-)Low Power Hardware Implementations from Data Flow Specifications by Integration of Emerging FeFET Technology (HiLoDa Nets) March 1, 2024 - March 1, 2027

Involved external institutions

Université Claude Bernard Lyon 1 (UCB) FR France (FR)

How to cite

APA:

Darne, B., Karim, A., Matrangolo, P.-A., Falk, J., O'Connor, I., Marchand, C.,... Teich, J. (2025). FeMFET-based High Performance, Ultra-Low Power Memory Cells for Reliable State Retention of Dataflow Networks. In Proceedings of the 38th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (pp. 1-8). Barcelona, Spain, ES.

MLA:

Darne, Basile, et al. "FeMFET-based High Performance, Ultra-Low Power Memory Cells for Reliable State Retention of Dataflow Networks." Proceedings of the 38th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Barcelona, Spain 2025. 1-8.

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