CSD-Driven Speedup in RISC-V Processor
Ebrahimiazandaryani F, Fey D (2025)
Publication Language: English
Publication Type: Conference contribution
Publication year: 2025
Journal
Publisher: Springer
Series: Lecture Notes in Computer Science
City/Town: Cham
Book Volume: 15569
Pages Range: 3-15
Conference Proceedings Title: Design and Architecture for Signal and Image Processing. 18th International Workshop, DASIP 2025, Barcelona, Spain, January 20–22, 2025, Proceedings
Event location: Barcelona
ISBN: 9783031878961
DOI: 10.1007/978-3-031-87897-8_1
Abstract
This paper introduces a synthesizable μ-architectural design method to boost the performance of a given RISC-V processor architecture by utilizing Canonical Signed Digit (CSD) representation during the execution stage within the processor pipeline. CSD is a unique ternary number system that enables carry/borrow-free addition/subtraction in constant time O(1) regardless of word length N. The CSD extension is exemplarily demonstrated to the Potato processor, a simple RISC-V implementation for FPGAs. However, the method can also be applied to other implementations in principle. Our performance boost due to the CSD requires an overhead for conversion between binary and CSD representation. This overhead is compensated by an extension to a seven-stage pipeline architecture, featuring a three-step execution stage that increases the throughput and the operating frequency and enables loop unrolling, which is especially advantageous in applications with consecutive calculations, e.g., signal processing. By experimental results, we compared our CSD-based ternary solution to the original implementation, which utilizes the usual pure binary number representation of the operands. Our approach achieved a 2.41X increase in operating frequency over the original RISC-V processor on FPGA, with over 20% of this gain attributed to the CSD encoding. This enhancement resulted in up to a 2.40X improvement in throughput and a 2.37X reduction in execution time for computation-intensive benchmark applications.
Authors with CRIS profile
Farhad Ebrahimiazandaryani
Lehrstuhl für Informatik 3 (Rechnerarchitektur)
Dietmar Fey
Lehrstuhl für Informatik 3 (Rechnerarchitektur)
How to cite
APA:
Ebrahimiazandaryani, F., & Fey, D. (2025). CSD-Driven Speedup in RISC-V Processor. In Jordane Lorandel, Ahmed Kamaleldin (Eds.), Design and Architecture for Signal and Image Processing. 18th International Workshop, DASIP 2025, Barcelona, Spain, January 20–22, 2025, Proceedings (pp. 3-15). Barcelona, ES: Cham: Springer.
MLA:
Ebrahimiazandaryani, Farhad, and Dietmar Fey. "CSD-Driven Speedup in RISC-V Processor." Proceedings of the 18th International Workshop on Design and Architecture for Signal and Image Processing, DASIP 2025, Barcelona Ed. Jordane Lorandel, Ahmed Kamaleldin, Cham: Springer, 2025. 3-15.
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