Analyzing performance portability for a SYCL implementation of the 2D shallow water equations
Büttner M, Alt C, Kenter T, Köstler H, Plessl C, Aizinger V (2025)
Publication Type: Journal article
Publication year: 2025
Journal
Book Volume: 81
Article Number: 772
Issue: 6
DOI: 10.1007/s11227-025-07063-7
Abstract
SYCL is an open standard for targeting heterogeneous hardware from C++. In this work, we evaluate a SYCL implementation for a discontinuous Galerkin discretization of the 2D shallow water equations targeting CPUs, GPUs, and also FPGAs. The discretization uses polynomial orders zero to two on unstructured triangular meshes. Separating memory accesses from the numerical code allow us to optimize data accesses for the target architecture. A performance analysis shows good portability across x86 and ARM CPUs, GPUs from different vendors, and even two variants of Intel Stratix 10 FPGAs. Measuring the energy to solution shows that GPUs yield an up to 10x higher energy efficiency in terms of degrees of freedom per joule compared to CPUs. With custom designed caches, FPGAs offer a meaningful complement to the other architectures with particularly good computational performance on smaller meshes. FPGAs with High Bandwidth Memory are less affected by bandwidth issues and have similar energy efficiency as latest generation CPUs.
Authors with CRIS profile
Christoph Alt
Lehrstuhl für Informatik 10 (Systemsimulation) (LSS)
Harald Köstler
Lehrstuhl für Informatik 10 (Systemsimulation) (LSS)
Involved external institutions
Germany (DE)How to cite
APA:
Büttner, M., Alt, C., Kenter, T., Köstler, H., Plessl, C., & Aizinger, V. (2025). Analyzing performance portability for a SYCL implementation of the 2D shallow water equations. Journal of Supercomputing, 81. https://doi.org/10.1007/s11227-025-07063-7
MLA:
Büttner, Markus, et al. "Analyzing performance portability for a SYCL implementation of the 2D shallow water equations." Journal of Supercomputing 81 (2025).
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