RISC-V CPU Design Using RRAM-CMOS Standard Cells

Fritscher M, Uhlmann M, Ostrovskyy P, Reiser D, Chen J, Wen J, Schulze C, Kahmen G, Fey D, Reichenbach M, Krstic M, Wenger C (2025)

Publication Type: Journal article

Publication year: 2025

Journal

IEEE Transactions on Very Large Scale Integration (Vlsi) Systems Institute of Electrical and Electronics Engineers (IEEE)

DOI: 10.1109/TVLSI.2025.3554476

Abstract

The breakdown of Dennard scaling has been the driver for many innovations such as multicore CPUs and has fueled the research into novel devices such as resistive random access memory (RRAM). These devices might be a means to extend the scalability of integrated circuits since they allow for fast and nonvolatile operation. Unfortunately, large analog circuits need to be designed and integrated in order to benefit from these cells, hindering the implementation of large systems. This work elaborates on a novel solution, namely, creating digital standard cells utilizing RRAM devices. Albeit this approach can be used both for small gates and large macroblocks, we illustrate it for a 2T2R-cell. Since RRAM devices can be vertically stacked with transistors, this enables us to construct a nand standard cell, which merely consumes the area of two transistors. This leads to a 25% area reduction compared to an equivalent CMOS nand gate. We illustrate achievable area savings with a half-adder circuit and integrate this novel cell into a digital standard cell library. A synthesized RISC-V core using RRAM-based cells results in a 10.7% smaller area than the equivalent design using standard CMOS gates.

Authors with CRIS profile

Dietmar Fey Lehrstuhl für Informatik 3 (Rechnerarchitektur)

Involved external institutions

Leibniz-Institut für innovative Mikroelektronik / IHP GmbH - Innovations for High Performance Microelectronics DE Germany (DE) Universität Rostock DE Germany (DE)

How to cite

APA:

Fritscher, M., Uhlmann, M., Ostrovskyy, P., Reiser, D., Chen, J., Wen, J.,... Wenger, C. (2025). RISC-V CPU Design Using RRAM-CMOS Standard Cells. IEEE Transactions on Very Large Scale Integration (Vlsi) Systems. https://doi.org/10.1109/TVLSI.2025.3554476

MLA:

Fritscher, Markus, et al. "RISC-V CPU Design Using RRAM-CMOS Standard Cells." IEEE Transactions on Very Large Scale Integration (Vlsi) Systems (2025).

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