Latency-Constrained Neural Architecture Search for U-Nets on Graphics Processing Units

Groth S, Heidorn C, Schmid M, Teich J, Hannig F (2025)

Publication Language: English

Publication Type: Conference contribution, Conference Contribution

Publication year: 2025

Publisher: VDE

Pages Range: 52-60

Conference Proceedings Title: Proceedings of the 28th Workshop on Methods and Description Languages for Modelling and Verification of Circuits and Systems (MBMV),

Event location: Rostock DE

ISBN: 978-3-8007-6515-7

Abstract

Neural Architecture Search (NAS) is a crucial process for finding novel neural networks for certain tasks. For real-time applications, it is beneficial to incorporate latency constraints already into the search process. One common way to realize NAS is to use multi-objective Bayesian optimization to find candidate neural architectures, which are then trained. Because training models is very time-consuming, we propose an approach that restricts search spaces using a method to estimate the inference time of neural architectures, thus only considering models that are below or close to the required inference time. We show that our approach reduces the time to evaluate points in the search space and, therefore, the whole NAS by multiple orders of magnitude while finding neural architectures of similar quality. Furthermore, we evaluate our approach using a zero-shot proxy that indicates a model’s quality without training the model. Here, we not only find the best architecture given the zero-shot proxy, but also reason about the limitations of the zero-shot proxy using our approach.

Authors with CRIS profile

Stefan Groth Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Christian Heidorn Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Frank Hannig Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Involved external institutions

Siemens AG, Healthcare Sector DE Germany (DE)

How to cite

APA:

Groth, S., Heidorn, C., Schmid, M., Teich, J., & Hannig, F. (2025). Latency-Constrained Neural Architecture Search for U-Nets on Graphics Processing Units. In Proceedings of the 28th Workshop on Methods and Description Languages for Modelling and Verification of Circuits and Systems (MBMV), (pp. 52-60). Rostock, DE: VDE.

MLA:

Groth, Stefan, et al. "Latency-Constrained Neural Architecture Search for U-Nets on Graphics Processing Units." Proceedings of the 28th Workshop on Methods and Description Languages for Modelling and Verification of Circuits and Systems (MBMV), Rostock VDE, 2025. 52-60.

BibTeX: Download