Mapping and Execution of Nested Loops on Processor Arrays: CGRAs vs. TCPAs

Walter D, Halm M, Seidel D, Ghosh I, Heidorn C, Hannig F, Teich J (2025)

Publication Status: In review

Publication Type: Unpublished / Preprint

Future Publication Type: Journal article

Publication year: 2025

DOI: 10.48550/arXiv.2502.12062

Open Access Link: https://arxiv.org/abs/2502.12062

Authors with CRIS profile

Dominik Walter Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Christian Heidorn Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Frank Hannig Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

How to cite

APA:

Walter, D., Halm, M., Seidel, D., Ghosh, I., Heidorn, C., Hannig, F., & Teich, J. (2025). Mapping and Execution of Nested Loops on Processor Arrays: CGRAs vs. TCPAs. (Unpublished, In review).

MLA:

Walter, Dominik, et al. Mapping and Execution of Nested Loops on Processor Arrays: CGRAs vs. TCPAs. Unpublished, In review. 2025.

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