Exploration of Clock and Power Gating Tradeoffs for the Design of Self-Powering Dataflow Networks

Karim A, Falk J, Teich J (2025)

Publication Language: English

Publication Type: Conference contribution, Conference Contribution

Publication year: 2025

Publisher: VDE VERLAG

City/Town: Berlin - Offenbach

Pages Range: 1-10

Event location: Rostock Warnemünde DE

Abstract

Dataflow networks are used for specification, modeling, analysis, and implementation of stream processing applications in either software, hardware, or mixed form. Applications of interest include signal and image processing. Particularly in the context of IoT systems, such applications often face high processing speed demands amidst limited power budgets (e.g., battery or ambient-powered scenarios). While these constraints may appear contradictory at first glance, recent research has brought up the concept of ’Self-Powering Dataflow Networks’ that exploits phases of unavailability of data to power down hardware components of a network consciously to save energy. This paper presents techniques to integrate clock as well as power-gating techniques when implementing dataflow networks completely in hardware. Analyzed are the total amount of power that may be saved and the overheads associated with implementing such techniques on ASICs. Finally, for different applications ranging from numeric iterative algorithms to signal and image processing dataflow networks, we evaluate the overall achievable power savings based on characterizations of power consumption of each synthesized actor and varying the frequency of arrival of data and intermittency properly. The evaluation is performed for different technology corners and also includes any impact on achievable performance in terms of throughput when applying such fine-grained (actor-based) power management techniques. As a major result, it is shown that the introduction of actor-based clock gating can achieve a high percentage in power savings compared to an always-on hardware implementation at no decline in throughput for dataflow networks with acyclic topology. For implementations in a technology suffering from high static power consumption, power-gating techniques can be used in combination, but with hardware overheads increasing with the amount of data that needs to be persisted in retention memories before any shutdown. Moreover, particularly for cyclic dataflow networks, declines in  throughput can also result due to longer shutdown and wakeup latencies.

Authors with CRIS profile

Abrarul Karim Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Joachim Falk Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Related research project(s)

Automatic Cross-Layer Synthesis of High Performance, (Ultra-)Low Power Hardware Implementations from Data Flow Specifications by Integration of Emerging FeFET Technology (HiLoDa Nets) March 1, 2024 - March 1, 2027 SystemCoDesigner: System level design space exploration for embedded systems (SystemCoDesigner) April 1, 2005 - April 1, 2008

How to cite

APA:

Karim, A., Falk, J., & Teich, J. (2025). Exploration of Clock and Power Gating Tradeoffs for the Design of Self-Powering Dataflow Networks. In VDE ITG; VDE/VDI GMM; GI (Eds.), Proceedings of the 28. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) (pp. 1-10). Rostock Warnemünde, DE: Berlin - Offenbach: VDE VERLAG.

MLA:

Karim, Abrarul, Joachim Falk, and Jürgen Teich. "Exploration of Clock and Power Gating Tradeoffs for the Design of Self-Powering Dataflow Networks." Proceedings of the 28. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Rostock Warnemünde Ed. VDE ITG; VDE/VDI GMM; GI, Berlin - Offenbach: VDE VERLAG, 2025. 1-10.

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