Scheller K, Engelmann A, Probst F, Flohr M, Weigel R, Schrotz AM, Fischer G (2024)
Publication Type: Conference contribution, Conference Contribution
Publication year: 2024
Publisher: IEEE
ISBN: 979-8-3503-6354-8
URI: https://ieeexplore.ieee.org/document/10867723
DOI: 10.1109/APMC60911.2024.10867723
This paper presents a compact, low DC-power four-stage G-Band power amplifier (PA) integrated into a 22 nm fully-depleted silicon-on-insulator (FDSOI) technology. The three common-source driver stages and the output stage utilize the capacitive neutralization technique for gain-boosting. The output stage is implemented as a tuned stacked-FET amplifier for further gain and output power enhancement. Low-loss stacked transformers are employed as matching networks to achieve a small core-area footprint of 0.024 mm2. The PA attains a gain of 12.5 dB, a 1 dB output compression point OP1dB of -4 dBm, and an extrapolated saturated output power Psat of 3.7 dB at 200 GHz, based on simulation and measurement. Supplied by 1.6 and 0.85 V, the circuit´s DC-power consumption is below 57 mW.
APA:
Scheller, K., Engelmann, A., Probst, F., Flohr, M., Weigel, R., Schrotz, A.-M., & Fischer, G. (2024). A 200 GHz Area-Efficient 4-stage Power Amplifier with Stacked Output Stage in 22 nm FDSOI. In Proceedings of the 2024 Asia-Pacific Microwave Conference. Bali, ID: IEEE.
MLA:
Scheller, Kai, et al. "A 200 GHz Area-Efficient 4-stage Power Amplifier with Stacked Output Stage in 22 nm FDSOI." Proceedings of the 2024 Asia-Pacific Microwave Conference, Bali IEEE, 2024.
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