Area-Efficient Digital Design Using RRAM-CMOS Standard Cells

Fritscher M, Uhlmann M, Ostrovskyy P, Reiser D, Chen J, Schubert A, Schulze C, Kahmen G, Fey D, Reichenbach M, Krstic M, Wenger C (2024)

Publication Language: English

Publication Type: Conference contribution

Publication year: 2024

Publisher: IEEE Computer Society

Pages Range: 81-87

Conference Proceedings Title: 2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

Event location: Knoxville, TN US

ISBN: 979-8-3503-5412-6

DOI: 10.1109/ISVLSI61997.2024.00026

Abstract

Extending the scalability of digital integrated circuits through novel device concepts is an attractive option. Among these concepts, resistive random access memory (RRAM) devices allow fast and nonvolatile operation. However, building large memristive systems is still challenging since large analog circuits have to be designed and integrated. In this paper, we propose a novel solution - the implementation of digital standard cells by the means of RRAM devices. While this methodology is universal, with applications ranging from few-device-circuits to large macroblocks, we demonstrate it for a 2T2R-cell. The benefits of using RRAM devices are demonstrated by implementing a NAND standard cell merely consuming the area of two transistors. This cell is about 25 % smaller than the equivalent CMOS NAND in the same technology. We use these cells to implement a half adder, beating the area of the equivalent CMOS implementation using more sophisticates gates by 15 %. Lastly, we fully integrate this novel standard cell into a digital standard cell library and perform a synthesis and layout of a RISC-V CPU core.

Authors with CRIS profile

Dietmar Fey Lehrstuhl für Informatik 3 (Rechnerarchitektur)

Involved external institutions

Leibniz-Institut für innovative Mikroelektronik / IHP GmbH - Innovations for High Performance Microelectronics DE Germany (DE) Universität Rostock DE Germany (DE)

How to cite

APA:

Fritscher, M., Uhlmann, M., Ostrovskyy, P., Reiser, D., Chen, J., Schubert, A.,... Wenger, C. (2024). Area-Efficient Digital Design Using RRAM-CMOS Standard Cells. In Himanshu Thapliyal, Jurgen Becker (Eds.), 2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (pp. 81-87). Knoxville, TN, US: IEEE Computer Society.

MLA:

Fritscher, Markus, et al. "Area-Efficient Digital Design Using RRAM-CMOS Standard Cells." Proceedings of the 2024 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2024, Knoxville, TN Ed. Himanshu Thapliyal, Jurgen Becker, IEEE Computer Society, 2024. 81-87.

BibTeX: Download