StencilStream: A SYCL-based Stencil Simulation Framework Targeting FPGAs

Opdenhövel JO, Alt C, Plessl C, Kenter T (2024)

Publication Type: Conference contribution

Publication year: 2024

Publisher: Institute of Electrical and Electronics Engineers Inc.

Pages Range: 100-108

Conference Proceedings Title: Proceedings - 2024 34th International Conference on Field-Programmable Logic and Applications, FPL 2024

Event location: Torino, ITA

ISBN: 9798331530075

DOI: 10.1109/FPL64840.2024.00023

Abstract

Although High-Level Synthesis has dramatically improved the usability of FPGAs in High-Performance Computing applications, it still requires much experience to create well-performing FPGA designs. We introduce the stencil simulation framework StencilStream to separate the concerns of performance engineers and domain scientists. We have formulated our performance-oriented stencil simulation designs for FPGAs along with their management code as C++ templates using SYCL language features. Application developers instantiate these templates with their concrete stencil code and obtain a complete application with little management overhead. In this work, we describe the most interesting API features and the two backend architectures of StencilStream, along with their corresponding performance models. We then evaluate the performance of the architectures using three manually implemented sample applications and highlight the real-world usability of StencilStream further with shallow water simulations obtained from a code-generation flow. Compiled with Intel oneAPI for an Intel Stratix 10 GX 2800 target FPGA, the best-performing sample design exceeds a throughput of 1 TFLOPS.

Involved external institutions

Universität Paderborn DE Germany (DE)

How to cite

APA:

Opdenhövel, J.O., Alt, C., Plessl, C., & Kenter, T. (2024). StencilStream: A SYCL-based Stencil Simulation Framework Targeting FPGAs. In Proceedings - 2024 34th International Conference on Field-Programmable Logic and Applications, FPL 2024 (pp. 100-108). Torino, ITA: Institute of Electrical and Electronics Engineers Inc..

MLA:

Opdenhövel, Jan Oliver, et al. "StencilStream: A SYCL-based Stencil Simulation Framework Targeting FPGAs." Proceedings of the 34th International Conference on Field-Programmable Logic and Applications, FPL 2024, Torino, ITA Institute of Electrical and Electronics Engineers Inc., 2024. 100-108.

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