Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs

Sabih M, Karim A, Wittmann J, Hannig F, Teich J (2024)

Publication Language: English

Publication Type: Conference contribution, Conference Contribution

Publication year: 2024

Pages Range: 1-9

Conference Proceedings Title: Proceedings of International Conference on Field Programmable Technology (FPT)

Event location: Sydney, Australia AU

ISBN: 979-8-3315-2321-3

DOI: 10.1109/ICFPT64416.2024.11113397

Authors with CRIS profile

Muhammad Sabih Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Abrarul Karim Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Frank Hannig Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Related research project(s)

Neural Approximate Accelerator Architecture Optimization for DNN Inference on Lightweight FPGAs (NA³Os) May 1, 2024 - April 30, 2027 Open-Source Design Tools for the Co-Development of AI Algorithms and AI Chips (DI-EDAI) May 1, 2024 - April 30, 2027

How to cite

APA:

Sabih, M., Karim, A., Wittmann, J., Hannig, F., & Teich, J. (2024). Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs. In IEEE (Eds.), Proceedings of International Conference on Field Programmable Technology (FPT) (pp. 1-9). Sydney, Australia, AU.

MLA:

Sabih, Muhammad, et al. "Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs." Proceedings of the International Conference on Field Programmable Technology (FPT), Sydney, Australia Ed. IEEE, 2024. 1-9.

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