ALPACA: An Accelerator Chip for Nested Loop Programs

Walter D, Brand M, Heidorn C, Witterauf M, Hannig F, Teich J (2024)

Publication Type: Conference contribution, Conference Contribution

Publication year: 2024

Conference Proceedings Title: Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)

Event location: Singapore SG

URI: https://ieeexplore.ieee.org/document/10558549

DOI: 10.1109/ISCAS58744.2024.10558549

Authors with CRIS profile

Dominik Walter Sonderforschungsbereich/Transregio 89 Invasives Rechnen Marcel Brand Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Christian Heidorn Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Michael Witterauf Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Frank Hannig Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

How to cite

APA:

Walter, D., Brand, M., Heidorn, C., Witterauf, M., Hannig, F., & Teich, J. (2024). ALPACA: An Accelerator Chip for Nested Loop Programs. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS). Singapore, SG.

MLA:

Walter, Dominik, et al. "ALPACA: An Accelerator Chip for Nested Loop Programs." Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Singapore 2024.

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