Kohlhepp B, Faber S, Kübrich D, Dürbaum T (2023)
Publication Language: English
Publication Type: Conference contribution, Conference Contribution
Publication year: 2023
Publisher: IEEE
Event location: Aalborg, Denmark
DOI: 10.23919/EPE23ECCEEurope58414.2023.10264516
Commutation loop inductance is on everyone’s lips in power electronics, due the relevance for switching transitions and switching losses. In most cases, this inductance is obtained by using numerical field simulations. However, confidence in the simulation results requires validation by measurements. Especially for designs employing wide bandgap semiconductors, minimized commutation loop inductance is crucial for full performance of the semiconductors. Applying optimized packages and PCB layouts results in commutation loop inductances below 1 nH, which makes its experimental extraction challenging. Therefore, the paper studies a method for commutation inductance measurement based on a resonance of a modified DC-link capacitor with this inductance. The measurement of a GaN-half-bridge’s commutation loop complies with results from simulation, demonstrating that the measurement method is applicable for commutation inductance in sub-nH range.
APA:
Kohlhepp, B., Faber, S., Kübrich, D., & Dürbaum, T. (2023). PCB Layout Parasitics Extraction of a GaN Half-Bridge: Simulation and Experimental Validation. In Proceedings of the 25th European Conference on Power Electronics and Applications (EPE'23 ECCE Europe). Aalborg, Denmark: IEEE.
MLA:
Kohlhepp, Benedikt, et al. "PCB Layout Parasitics Extraction of a GaN Half-Bridge: Simulation and Experimental Validation." Proceedings of the 25th European Conference on Power Electronics and Applications (EPE'23 ECCE Europe), Aalborg, Denmark IEEE, 2023.
BibTeX: Download