PARASITIC INDUCTANCE AND CURRENT SPREADING OF PARALLELED SiC MOSFETs ANALYSED BY IMPEDANCE MODELLING
Apelsmeier A, März M (2023)
Publication Type: Conference contribution, Conference Contribution
Subtype: other
Publication year: 2023
Book Volume: 2023
Pages Range: 233-240
Event location: Bruessel
Journal Issue: 17
Abstract
Paralleling silicon carbide metal-oxide semiconductor field-effect transistors in multichip power switches is a common way to achieve the required current rating in high power converters. The parasitic inductances, the static and dynamic current imbalance of the paralleled MOSFETs are limiting the maximum current and switching speed of the devices. This research investigates the effect, that the number of paralleled chips has on the parasitic inductance and the current balancing using analytical impedance analysis of lumped elements in the frequency domain. The proposed calculation approach is applied to identify the main design relevant parameters affecting the parasitic inductance and the layout-related current spreading. The results are verified with numerical parameter extractions and finite element analyses.
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How to cite
APA:
Apelsmeier, A., & März, M. (2023). PARASITIC INDUCTANCE AND CURRENT SPREADING OF PARALLELED SiC MOSFETs ANALYSED BY IMPEDANCE MODELLING. In Proceedings of the International Conference on Power Electronics, Machines and Drives (PEMD 2023) (pp. 233-240). Bruessel, BE.
MLA:
Apelsmeier, Andreas, and Martin März. "PARASITIC INDUCTANCE AND CURRENT SPREADING OF PARALLELED SiC MOSFETs ANALYSED BY IMPEDANCE MODELLING." Proceedings of the International Conference on Power Electronics, Machines and Drives (PEMD 2023), Bruessel 2023. 233-240.
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