Trautmann J, Krüger P, Becher A, Wildermann S, Teich J (2023)
Publication Language: English
Publication Type: Journal article, Editorial
Publication year: 2023
Pages Range: 1-27
URI: https://dl.acm.org/doi/10.1145/3635719
DOI: 10.1145/3635719
Digitizing side-channel signals at high sampling rates produces huge amounts of data, while side-channel analysis techniques only need those specific trace segments containing Cryptographic Operations (COs). For detecting these segments, waveform-matching techniques have been established comparing the signal with a template of the CO's characteristic pattern. Real-time waveform matching requires highly parallel implementations as achieved by hardware design but also reconfigurability as provided by FPGAs to adapt the matching hardware to a specific CO pattern. However, currently proposed designs process the samples from analog-to-digital converters sequentially and can only process low sampling rates due to the limited clock speed of FPGAs.
In this paper, we present a parallel waveform-matching architecture capable of performing high-speed waveform matching on a high-end FPGA-based digitizer. We also present a workflow for calibrating the waveform-matching system to the specific pattern of the CO in the presence of hardware restrictions provided by the FPGA hardware. Our implementation enables waveform matching at 10 GS/s, offering a speedup of 50x compared to the fastest state-of-the-art implementation known to us. We demonstrate how to apply the technique for attacking the widespread XTS-AES algorithm using waveform matching to recover the encrypted tweak even in the presence of so-called systemic noise.
APA:
Trautmann, J., Krüger, P., Becher, A., Wildermann, S., & Teich, J. (2023). Design, Calibration, and Evaluation of Real-Time Waveform Matching on an FPGA-based Digitizer at 10 GS/s. ACM Transactions on Reconfigurable Technology and Systems, 1-27. https://doi.org/10.1145/3635719
MLA:
Trautmann, Jens, et al. "Design, Calibration, and Evaluation of Real-Time Waveform Matching on an FPGA-based Digitizer at 10 GS/s." ACM Transactions on Reconfigurable Technology and Systems (2023): 1-27.
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