Clock-Tree–Aware Resource-Consumption Models for Embedded SoC Platforms

Dengler E (2022)

Publication Language: English

Publication Type: Thesis

Publication year: 2022


As of today, more and more applications with both timing and energy constraints arise in embedded platforms. A famous example of such a platform is an artificial cardiac pacemaker. It has a safety-critical timing constraint, but also requires appropriate energy management to ensure the battery lasts until the next charging date in any case. To be able to give guarantees regarding these requirements, Worst-Case Execution Time (WCET) and Worst-Case Energy Consumption (WCEC) analyses are necessary to determine an upper bound of time and energy consumption. To make the recharging procedures as infrequent as possible, achieving the minimum energy consumption at a given timing constraint is the goal.
There are two main options to save energy in energy-constrained real-time systems: Either a component, e.g., the CPU or a peripheral device, is turned off entirely if not needed, or it operates at a lower speed. As a consequence, the system may need more time to complete its current task but uses less power. While a different component setting can save power, one has to consider that there are penalties regarding runtime and power consumption for the platform reconfiguration, which can outweigh the benefit of the lower consumption for both time behaviour and energy consumption. This applies to the main processing unit as well as peripheral devices on an embedded microcontroller. In addition, the activated and used peripherals can have a massive impact on these parameters, as well as the frequency these are running at. All these configuration options are based on the clock tree of the embedded chip, which is used to convert the input clocks to the required output signals for the CPU or peripheral devices.
Two objectives arise from this problem description and are dealt with in this work: First, this thesis develops a mathematical model to determine the energy-optimal solution of a sequential set of tasks for a given hardware platform, which still gives guarantees regarding the execution time of the program. It considers the theoretical WCET and the available clock-tree configurations for required frequency and device configurations for each task, the corresponding power consumption, a periodic deadline for the program, and the penalties for changing between different clock-tree configurations to determine the best possible solution for the set of tasks. The second objective is to check whether this model can be used to determine the minimal power consumption of real hardware for a given set of tasks. Therefore, a hardware model is created for a hardware platform, the ESP32-C3 (a RISC-V single-core microprocessor), and integrated into the open-source analysis tool PLATIN. This model is validated with a benchmark suite and compared to external time measurements. Finally, power consumption measurements were performed for the ESP32-C3, and the energy-optimal solutions for two example tasks are determined with the mathematical model. In comparison to a pessimistic approach that does not selectively reconfigure clock trees the optimisations achieved significant energy savings.

Authors with CRIS profile

Related research project(s)

How to cite


Dengler, E. (2022). Clock-Tree–Aware Resource-Consumption Models for Embedded SoC Platforms (Master thesis).


Dengler, Eva. Clock-Tree–Aware Resource-Consumption Models for Embedded SoC Platforms. Master thesis, 2022.

BibTeX: Download