Hosseinzadeh Foroushani S, Klemm M, Fischer G, Fey D (2023)
Publication Type: Journal article, Original article
Publication year: 2023
Open Access Link: https://www.degruyter.com/document/doi/10.1515/itit-2023-0022/html
Abstract : With decreasing die size and the ability to store multiple bits in a single cell, resistive random access mem-
ory (ReRAM) can be used to increase storage density, making it a promising technology for the next generation of
memory. However, multi-level write operations suffer from impairments such as large latency, high energy consump-
tion, and reliability issues. In this paper, we study different mechanisms affecting the “multi-level incremental step
pulse with verify algorithm” (M-ISPVA) on a 1-transistor-1-resistor (1T1R) model in transient simulation at the com-
ponent and the circuit level with focus on resistance control and energy consumption during the entire process of
state transitions. By dividing the M-ISPVA into a triggering and a controlling period, we discovered the transis-
tor to operate in the ohmic region during the triggering period as a voltage-controlled resistance and in the satu-
ration region during the controlling period as a voltage-controlled current limiter. Controlling the gate voltage in the triggering period can move the triggering point to a desired write voltage and in the controlling period can increase or decrease resistance steps per pulse to attain a desired speed of resistance change. In addition, the major energy portion
is consumed for reset operation during triggering and for set operation during the controlling period. To optimize
write performance, extra precaution must be taken when defining resistance states with target read-out current and
gate voltage with the focus on evenly balanced latencies between all transitions. A direct multi-level write operation
shows 67.5 % latency and 62.5 % energy saving compared to indirect ones, but suffers from only unidirectional control,
making it non-feasible. In case of a 4 k bit memory, the more reliable M-ISPVA faces almost 37 % higher latency and
energy compared to the basic ISPVA.
APA:
Hosseinzadeh Foroushani, S., Klemm, M., Fischer, G., & Fey, D. (2023). Optimizing multi-level ReRAM memory for low latency and low energy consumption. it - Information Technology. https://doi.org/10.1515/itit-2023-0022
MLA:
Hosseinzadeh Foroushani, Shima, et al. "Optimizing multi-level ReRAM memory for low latency and low energy consumption." it - Information Technology (2023).
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