Reducing OpenMP to FPGA Round-trip Times with Predictive Modelling [Data set]

Brandner J, Mayer F, Philippsen M (2022)

Publication Language: English

Publication Type: Other publication type, Forschungsdaten

Publication year: 2022

Book Volume: Zenodo

DOI: 10.5281/zenodo.7534795

Open Access Link: https://doi.org/10.5281/zenodo.7534795

Abstract

This archive contains the samples generated for the conference paper "Reducing OpenMP to FPGA Round-trip Times with Predictive Modelling" (In Proc. 18th Intl. Workshop on OpenMP (IWOMP), Chattanooga, TN, Sept. 2022, Springer LNCS vol. 13527, pp. 94–108, https://doi.org/10.1007/978-3-031-15922-0_7).

Authors with CRIS profile

Julian Brandner Lehrstuhl für Informatik 2 (Programmiersysteme) Florian Mayer Lehrstuhl für Informatik 2 (Programmiersysteme) Michael Philippsen Lehrstuhl für Informatik 2 (Programmiersysteme)

Related research project(s)

OpenMP for reconfigurable heterogenous architectures (ORKA) OpenMP für rekonfigurierbare heterogene Architekturen Nov. 1, 2017 - Dec. 31, 2023

How to cite

APA:

Brandner, J., Mayer, F., & Philippsen, M. (2022). Reducing OpenMP to FPGA Round-trip Times with Predictive Modelling [Data set].

MLA:

Brandner, Julian, Florian Mayer, and Michael Philippsen. Reducing OpenMP to FPGA Round-trip Times with Predictive Modelling [Data set]. 2022.

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