Majority Logic Based In-Memory Comparator
Lakshmi V, Prabahar JR, Pudi V (2022)
Publication Type: Conference contribution
Publication year: 2022
Publisher: Institute of Electrical and Electronics Engineers Inc.
Book Volume: 2022-August
Pages Range: 105-108
Conference Proceedings Title: IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE
Event location: Virtual, Kuala Lumpur, MYS
ISBN: 9781665482455
DOI: 10.1109/ICSE56004.2022.9863155
Abstract
To conquer the von Neumann bottleneck, it is necessary to shift computation to the place where data resides. In this work, we present a methodology to move the comparator circuit to the memory array. A binary comparator is implemented in a transistor-accessed ReRAM (Resistive Random Access Mem-ory) array using majority logic. The majority primitive is a better logic primitive than NAND/NOR/IMPLY primitives for arithmetic intensive operations and also can be realized in memory array efficiently as a READ operation. Using Majority gates and vast gate-level parallelism in the array, comparator is implemented optimally, latency and energy-wise. Using the methodology presented for 1-bit and 8-bit, any n-bit comparator can be realized in 6 + 4log2n cycles. Moreover, a general transistor-accessed memory array can be used to implement the proposed comparator without the need for any supreme modifications to the memory peripherals and is efficient as well in terms of energy.
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APA:
Lakshmi, V., Prabahar, J.R., & Pudi, V. (2022). Majority Logic Based In-Memory Comparator. In IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE (pp. 105-108). Virtual, Kuala Lumpur, MYS: Institute of Electrical and Electronics Engineers Inc..
MLA:
Lakshmi, Vijaya, John Reuben Prabahar, and Vikramkumar Pudi. "Majority Logic Based In-Memory Comparator." Proceedings of the 2022 IEEE International Conference on Semiconductor Electronics, ICSE 2022, Virtual, Kuala Lumpur, MYS Institute of Electrical and Electronics Engineers Inc., 2022. 105-108.
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