Employing Polyhedral Methods to Reduce Data Movement in FPGA Stencil Codes

Mayer F, Brandner J, Philippsen M (2023)

Publication Language: English

Publication Type: Conference contribution, Conference Contribution

Publication year: 2023

Publisher: Springer International Publishing

Series: Lecture Notes in Computer Science (LNCS)

City/Town: Cham

Book Volume: 13829

Pages Range: 47-63

Conference Proceedings Title: Proc. of the 35rd Intl. Workshop on Languages and Compilers for Parallel Computing (LCPC 2022)

Event location: Chicago, IL US

ISBN: 978-3-031-31444-5

DOI: 10.1007/978-3-031-31445-2_4

Abstract

Due to the ubiquity of stencil codes in scientific computing there is a strong need to optimize their runtimes. When using a GPU as an accelerator, programmers need to amortize the cost of shipping data to/from the device. When using an FPGA as an accelerator, the situation is worse as programmers also need to build a cache-like data shipment on the device. To avoid this tedious and error-prone task, our source-to-source compiler takes OpenMP pragma-annotated stencil codes, derives a polyhedral model from them, finds and merges overlapping contiguous read accesses, and instruments the code with vendor-specific annotations that guide the FPGA synthesis to generate efficient stencil hardware with fast data shipment and fast on-FPGA cache-like structures. Our data movement optimization improves the runtime of a set of stencil codes from three different sources by between 1.3x and 5.8x, on average.

Authors with CRIS profile

Florian Mayer Lehrstuhl für Informatik 2 (Programmiersysteme) Julian Brandner Lehrstuhl für Informatik 2 (Programmiersysteme) Michael Philippsen Lehrstuhl für Informatik 2 (Programmiersysteme)

Related research project(s)

OpenMP for reconfigurable heterogenous architectures (ORKA) OpenMP für rekonfigurierbare heterogene Architekturen Nov. 1, 2017 - Dec. 31, 2023

How to cite

APA:

Mayer, F., Brandner, J., & Philippsen, M. (2023). Employing Polyhedral Methods to Reduce Data Movement in FPGA Stencil Codes. In Charith Mendis, Lawrence Rauchwerger (Eds.), Proc. of the 35rd Intl. Workshop on Languages and Compilers for Parallel Computing (LCPC 2022) (pp. 47-63). Chicago, IL, US: Cham: Springer International Publishing.

MLA:

Mayer, Florian, Julian Brandner, and Michael Philippsen. "Employing Polyhedral Methods to Reduce Data Movement in FPGA Stencil Codes." Proceedings of the Languages and Compilers for Parallel Computing (LCPC 2022), Chicago, IL Ed. Charith Mendis, Lawrence Rauchwerger, Cham: Springer International Publishing, 2023. 47-63.

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