Probst F, Engelmann A, Dietz M, Issakov V, Weigel R (2022)
Publication Language: English
Publication Status: Accepted
Publication Type: Conference contribution, Conference Contribution
Future Publication Type: Conference contribution
Publication year: 2022
Event location: Denver, Colorado
DOI: 10.1109/IMS37962.2022.9865592
This paper presents an area efficient, low-power pseudo-random binary sequence (PRBS) generator which is built of true single-phase-clock (TSPC) flip-flops that form a linear-feedback shift register (LFSR). Operating at a supply voltage of 0.88 V it can generate a 2¹¹-1 m-sequence with a maximum data rate of 33 Gb/s. The circuit is fabricated in a 22-nm fully depleted silicon on insulator (FDSOI) CMOS technology and occupies a core area of only 42 μm2. With a core power consumption of only 1.3 mW at the maximum data rate, it is well suited for its application as a baseband signal generator in a phase-modulated continuous-wave (PMCW) radar transmitter. The PRBS generator exhibits a figure of merit (FoM) of only 8 fJ/bit which represents an improvement by the factor of five compared to the current state of the art to the best of authors’ knowledge.
APA:
Probst, F., Engelmann, A., Dietz, M., Issakov, V., & Weigel, R. (2022). An Area Efficient Low-Power mmWave PRBS Generator in FDSOI. In Proceedings of the IEEE MTT-S International Microwave Symposium 2022. Denver, Colorado, US.
MLA:
Probst, Florian, et al. "An Area Efficient Low-Power mmWave PRBS Generator in FDSOI." Proceedings of the IEEE MTT-S International Microwave Symposium 2022, Denver, Colorado 2022.
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