Reuben JR (2021)
Publication Type: Journal article
Publication year: 2021
Book Volume: 11
Article Number: 45
Journal Issue: 4
Computational methods in memory array are being researched in many emerging memory technologies to conquer the ‘von Neumann bottleneck’. Resistive RAM (ReRAM) is a non-volatile memory, which supports Boolean logic operation, and adders can be implemented as a sequence of Boolean operations in the memory. While many in-memory adders have recently been proposed, their latency is exorbitant for increasing bit-width (O(n)). Decades of research in computer arithmetic have proven parallel-prefix technique to be the fastest addition technique in conventional CMOS-based binary adders. This work endeavors to move parallel-prefix addition to the memory array to significantly minimize the latency of in-memory addition. Majority logic was chosen as the fundamental logic primitive and parallel-prefix adders synthesized in majority logic were mapped to the memory array using the proposed algorithm. The proposed algorithm can be used to map any parallel-prefix adder to a memory array and mapping is performed in such a way that the latency of addition is minimized. The proposed algorithm enables addition in O(log(n)) latency in the memory array.
APA:
Reuben, J.R. (2021). Design of in-memory parallel-prefix adders. Journal of Low Power Electronics and Applications, 11(4). https://doi.org/10.3390/jlpea11040045
MLA:
Reuben, John Reuben. "Design of in-memory parallel-prefix adders." Journal of Low Power Electronics and Applications 11.4 (2021).
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