Design and Evaluation of a Tunable PUF Architecture for FPGAs

Streit FJ, Krüger P, Becher A, Wildermann S, Teich J (2021)

Publication Language: English

Publication Type: Conference contribution, Abstract of lecture

Publication year: 2021

Conference Proceedings Title: IEEE Proceedings of the 20th International Conference on Field-Programmable Technology

Event location: Auckland, New Zealand

DOI: 10.1109/ICFPT52863.2021

Abstract

FPGA-based Physical Unclonable Functions (PUFs) have emerged as a viable alternative to permanent key storage by turning effects of inaccuracies during the manufacturing process of a chip into a unique, FPGA-intrinsic secret. However, many fixed PUF designs may suffer from unsatisfactory statistical properties in terms of uniqueness, uniformity, and robustness. Moreover, a PUF signature may alter over time due to aging or changing operating conditions, rendering a PUF insecure in the worst case. As a remedy, we propose CHOICE, a novel class of FPGA-based PUF designs with tunable uniqueness and reliability characteristics. By the use of addressable shift registers available on an FPGA, we show that a wide configuration space for adjusting a device-specific PUF response is obtained without any sacrifice of randomness. In particular, we demonstrate the concept of address-tunable propagation delays, whereby we are able to increase or decrease the probability of obtaining ’1’s in the PUF response. Experimental evaluations on a group of six 28 nm Xilinx Artix-7 FPGAs show that CHOICE PUFs provide a large range of configurations to allow a fine-tuning to an average uniqueness between 49% and 51%, while simultaneously achieving bit error rates below 1.5%, thus outperforming state-of-the-art PUF designs. Moreover, with only a single FPGA slice per PUF bit, CHOICE is one of the smallest PUF designs currently available for FPGAs. It is well-known that signal propagation delays are affected by temperature, as the operating temperature impacts the internal currents of transistors that ultimately make up the circuit. We therefore comprehensively investigate how temperature variations affect the PUF response and demonstrate how the tunability of CHOICE enables us to determine configurations that show a high robustness to such variations. As a case study, we present a cryptographic key generation scheme based on CHOICE PUF responses as device-intrinsic secret and investigate the design objectives resource costs, performance, and temperature robustness to show the practicability of our approach.

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APA:

Streit, F.-J., Krüger, P., Becher, A., Wildermann, S., & Teich, J. (2021, December). Design and Evaluation of a Tunable PUF Architecture for FPGAs. Paper presentation at International Conference on Field-Programmable Technology (FPT), Auckland, New Zealand, NZ.

MLA:

Streit, Franz-Josef, et al. "Design and Evaluation of a Tunable PUF Architecture for FPGAs." Presented at International Conference on Field-Programmable Technology (FPT), Auckland, New Zealand 2021.

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