Device performance tuning of Ge gate-all-around tunneling field effect transistors by means of GeSn: Potential and challenges
Rolseth EG, Blech A, Fischer IA, Hashad Y, Koerner R, Kostecki K, Kruglov A, Senthilinivasan VS, Weiser M, Wendav T, Busch K, Schulze J (2017)
Publication Type: Conference contribution
Publication year: 2017
Publisher: Institute of Electrical and Electronics Engineers Inc.
Pages Range: 57-65
Conference Proceedings Title: 2017 40th International Convention on Information and Communication Technology, Electronics and Microelectronics, MIPRO 2017 - Proceedings
Event location: Opatija
ISBN: 9789532330922
DOI: 10.23919/MIPRO.2017.7973391
Abstract
In this paper we report experimental results on the fabrication and characterization of vertical Ge gate-all-around p-channel TFETs, utilizing GeSn as a channel material. Through two sample series, the potential and challenges of implementing the low-band gap material GeSn are reviewed. It is verified that ION can be effectively enhanced by increasing the Sn-content in the GeSn-channel, due to increasing tunneling probabilities. Further it is found that when limited to a 10 nm δ-layer, Ge0.96Sn0.04 is most beneficial for ION when positioned inside the channel as opposed to in the source, with a maximum of ION = 180 μA/μm at VDS= -2 V and VG = -4 V. Enhanced leakage currents (IOFF), which also degrades the subthreshold swing (SS), is a consequence of a smaller band gap and enhanced defect densities, and represent key challenges with implementing GeSn.
Authors with CRIS profile
Involved external institutions
Germany (DE)How to cite
APA:
Rolseth, E.G., Blech, A., Fischer, I.A., Hashad, Y., Koerner, R., Kostecki, K.,... Schulze, J. (2017). Device performance tuning of Ge gate-all-around tunneling field effect transistors by means of GeSn: Potential and challenges. In Marina Cicin-Sain, Filip Hormot, Tihana Galinac Grbac, Boris Vrdoljak, Edvard Tijan, Karolj Skala, Slobodan Ribaric, Stjepan Gros, Vlado Sruk, Mladen Mauher, Petar Biljanovic, Marko Koricic (Eds.), 2017 40th International Convention on Information and Communication Technology, Electronics and Microelectronics, MIPRO 2017 - Proceedings (pp. 57-65). Opatija, HU: Institute of Electrical and Electronics Engineers Inc..
MLA:
Rolseth, Erlend G., et al. "Device performance tuning of Ge gate-all-around tunneling field effect transistors by means of GeSn: Potential and challenges." Proceedings of the 40th International Convention on Information and Communication Technology, Electronics and Microelectronics, MIPRO 2017, Opatija Ed. Marina Cicin-Sain, Filip Hormot, Tihana Galinac Grbac, Boris Vrdoljak, Edvard Tijan, Karolj Skala, Slobodan Ribaric, Stjepan Gros, Vlado Sruk, Mladen Mauher, Petar Biljanovic, Marko Koricic, Institute of Electrical and Electronics Engineers Inc., 2017. 57-65.
BibTeX: Download