Letras M, Falk J, Teich J (2021)
Publication Language: English
Publication Type: Conference contribution, Conference Contribution
Publication year: 2021
Event location: München
This paper presents a new approach to estimate the throughput of real-world dataflow applications mapped to multi-core systems based on decision trees. Design Space Exploration (DSE) is employed to explore the mapping alternatives of a given application to a multi-core architecture to find the highest throughput solutions. Here, a fast evaluation of the throughput of a single implementation is required. However, simulation-based as well as measurement-based evaluation approaches impose often unaffordably high evaluation times. During a DSE, this evaluation time is particularly critical, as typically thousands of solutions need to be evaluated. Obviously, there exists a trade-off between evaluation accuracy and time for evaluating the throughput of an implementation. This paper presents a solution exploiting this trade-off by proposing a decision tree-based approach consisting of a trained decision tree model used as a throughput evaluator by the DSE. We show that a well-trained evaluator is able to estimate the throughput of an implementation about 20× faster than using a measurement-based evaluation. Moreover, in order to deliver a sufficient accuracy, our DSE approach uses decision tree-based valuations 90 % of the time and measurement-based evaluations for the remaining 10 %. On average, the resulting DSE approach is able to find Pareto-fronts about 8× faster than a reference DSE using measurements only with equal quality.
Letras, M., Falk, J., & Teich, J. (2021). Decision Tree-based Throughput Estimation to Accelerate Design Space Exploration for Multi-Core Applications. In Proceedings of the 24. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen. München.
Letras, Martin, Joachim Falk, and Jürgen Teich. "Decision Tree-based Throughput Estimation to Accelerate Design Space Exploration for Multi-Core Applications." Proceedings of the 24. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, München 2021.