TReMo: A Model for Ternary ReRAM-Based Memories with Adjustable Write-Verification Capabilities

Hosseinzadeh S, Biglari M, Fey D (2020)

Publication Language: English

Publication Type: Conference contribution, Original article

Publication year: 2020

Publisher: IEEE

Pages Range: 44-48

Conference Proceedings Title: 2020 23rd Euromicro Conference on Digital System Design (DSD)

ISBN: 978-1-7281-9535-3

URI: https://ieeexplore.ieee.org/document/9217865

DOI: 10.1109/DSD51259.2020.00019

Abstract

With the increasing use and advancement of memristors, implementation barriers for ternary systems, such as handling more than two states without any extra hardware, could be broken. In this paper, for the first time to the best of our knowledge, a new memory model on circuit level based on ReRAM is modeled for the ternary applications. This novel ternary memory model benefits from a parallel read method, for accomplishing low-latency read operation, and an often-used write-verification method. In addition, a thorough tool for this ternary memory is developed that performs energy, performance and area estimation which is an extension of the existing nonvolatile memory tool called NVSim.

Authors with CRIS profile

Shima Hosseinzadeh Foroushani Lehrstuhl für Informatik 3 (Rechnerarchitektur) Mehrdad Biglari Lehrstuhl für Informatik 3 (Rechnerarchitektur) Dietmar Fey Lehrstuhl für Informatik 3 (Rechnerarchitektur)

How to cite

APA:

Hosseinzadeh, S., Biglari, M., & Fey, D. (2020). TReMo: A Model for Ternary ReRAM-Based Memories with Adjustable Write-Verification Capabilities. In 2020 23rd Euromicro Conference on Digital System Design (DSD) (pp. 44-48). IEEE.

MLA:

Hosseinzadeh, Shima, Mehrdad Biglari, and Dietmar Fey. "TReMo: A Model for Ternary ReRAM-Based Memories with Adjustable Write-Verification Capabilities." Proceedings of the 2020 23rd Euromicro Conference on Digital System Design (DSD) IEEE, 2020. 44-48.

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