AnyHLS: High-Level Synthesis with Partial Evaluation

Özkan MA, Pérard-Gayot A, Membarth R, Slusallek P, Leißa R, Hack S, Teich J, Hannig F (2020)

Publication Type: Conference contribution

Publication year: 2020

Event location: Hamburg DE

URI: https://arxiv.org/pdf/2002.05796.pdf

DOI: 10.1109/tcad.2020.3012172

Abstract

FPGAs excel in low power and high throughput computations, but they are challenging to program. Traditionally, developers rely on hardware description languages like Verilog or VHDL to specify the hardware behavior at the register-transfer level. High-Level Synthesis (HLS) raises the level of abstraction, but still requires FPGA design knowledge. Programmers usually write pragma-annotated C/C++ programs to define the hardware architecture of an application. However, each hardware vendor extends its own C dialect using its own vendor-specific set of pragmas. This prevents portability across different vendors. Furthermore, pragmas are not first-class citizens in the language. This makes it hard to use them in a modular way or design proper abstractions. 

In this paper, we present AnyHLS, an approach to synthesize FPGA designs in a modular and abstract way. AnyHLS is able to raise the abstraction level of existing HLS tools by resorting to modern programming language features such as types and higher-order functions as follows: First, partial evaluation is used to specialize and to optimize the user application based on a library of abstractions. Finally, the backend of AnyHLS generates vendor-specific HLS code for Intel and Xilinx FPGAs. Portability is obtained by avoiding any vendor-specific pragmas at the source code. In order to validate achievable gains in productivity, a library for the domain of image processing is introduced as a case study, and its synthesis results are compared with several state-of-the-art DSL approaches for this domain.

Authors with CRIS profile

Mehmet Akif Özkan Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Frank Hannig Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Involved external institutions

Universität des Saarlandes (UdS) DE Germany (DE)

How to cite

APA:

Özkan, M.A., Pérard-Gayot, A., Membarth, R., Slusallek, P., Leißa, R., Hack, S.,... Hannig, F. (2020). AnyHLS: High-Level Synthesis with Partial Evaluation. In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS). Hamburg, DE.

MLA:

Özkan, Mehmet Akif, et al. "AnyHLS: High-Level Synthesis with Partial Evaluation." Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Hamburg 2020.

BibTeX: Download