Orthogonal Instruction Processing: An Alternative to Lightweight VLIW Processors

Brand M, Hannig F, Tanase AP, Teich J (2017)

Publication Language: English

Publication Type: Conference contribution, Original article

Publication year: 2017

Pages Range: 5-12

Conference Proceedings Title: 2017 IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip

Event location: Korea University, Seoul, Korea KR

ISBN: 978-1-5386-3441-7

DOI: 10.1109/MCSoC.2017.17

Abstract

We propose a new processor architecture called
Orthogonal Instruction Processing (OIP). Contrary to Very Long
Instruction Word (VLIW) decoding, we propose to orthogonally
decode the sub-instruction words of each Functional Unit (FU)
instead. Hereby, the OIP architecture is able to reduce the overall
machine code size of VLIW programs significantly. We will
show analytically as well as experimentally that, compared to
a VLIW processor, the savings in instruction memory size easily
compensate the overhead of one separate branch unit needed for
each FU.
For the analytical analysis, a mathematical model of hardware
costs of an OIP processor is developed and compared to a
conventional VLIW processor. In addition, we compare the code
size of selected representative programs of the new processor
architecture and show big savings of program memory. Here, the
instruction memory requirements can be decreased by a factor of
0.465. This decrease in instruction memory, despite the discussed
overhead, leads to savings in the overall hardware costs of one
processor by a factor of 0.989.

Authors with CRIS profile

Marcel Brand Sonderforschungsbereich/Transregio 89 Invasives Rechnen Frank Hannig Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Alexandru-Petru Tanase Sonderforschungsbereich/Transregio 89 Invasives Rechnen Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Related research project(s)

Invasive Tightly-Coupled Processor Arrays (B02) (SFB/TRR 89 InvasIC (B02)) DFG SFB/Transregio 89 "Invasive Computing" (TRR 89) July 1, 2010 - Dec. 31, 2022 DFG SFB/Transregio 89 "Invasive Computing" (TRR 89) July 1, 2010 - Dec. 31, 2022

How to cite

APA:

Brand, M., Hannig, F., Tanase, A.-P., & Teich, J. (2017). Orthogonal Instruction Processing: An Alternative to Lightweight VLIW Processors. In 2017 IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (pp. 5-12). Korea University, Seoul, Korea, KR.

MLA:

Brand, Marcel, et al. "Orthogonal Instruction Processing: An Alternative to Lightweight VLIW Processors." Proceedings of the IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-17), Korea University, Seoul, Korea 2017. 5-12.

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