A Power-Aware Behavioral Model of a Five-State Phase-Frequency Detector

Glock S, Fischer G, Weigel R, Ußmüller T (2011)

Publication Type: Conference contribution

Publication year: 2011

Publisher: IEEE

Pages Range: 1-4

Conference Proceedings Title: A Power-Aware Behavioral Model of a Five-State Phase-Frequency Detector

Event location: Melbourne, Australia

Abstract

This paper introduces a power-aware behavioral modeling approach for analog components. A Verilog-A behavioral model, which considers the component’s current consumption, is created using circuit information obtained from transistorlevel simulation. Therefore, the model features high accuracy with the benefit of low computational effort. The concept can be applied to any analog component and enables the simulation of complex analog systems. The approach is practically applied to the design of a phase-frequency detector, which determines important characteristics of a PLL.

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How to cite

APA:

Glock, S., Fischer, G., Weigel, R., & Ußmüller, T. (2011). A Power-Aware Behavioral Model of a Five-State Phase-Frequency Detector. In A Power-Aware Behavioral Model of a Five-State Phase-Frequency Detector (pp. 1-4). Melbourne, Australia: IEEE.

MLA:

Glock, Stefan, et al. "A Power-Aware Behavioral Model of a Five-State Phase-Frequency Detector." Proceedings of the A Power-Aware Behavioral Model of a Five-State Phase-Frequency Detector, Melbourne, Australia IEEE, 2011. 1-4.

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