Efficient reconfigurable on-chip buses for fpgas

Haubelt C, Koch D, Teich J (2008)

Publication Status: Published

Publication Type: Conference contribution, Conference Contribution

Publication year: 2008

Pages Range: 287-290

Article Number: 4724920

Conference Proceedings Title: Proceedings 16th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2008)

Event location: Palo Alto, California US

ISBN: 9780769533070

DOI: 10.1109/FCCM.2008.33

Abstract

This paper presents techniques for generating on-chip buses suitable for dynamically integrating hardware modules into an FPGA-based SoC by partial reconfiguration. The buses permit direct connections of master and slave modules to the bus in combination with a flexible fine-grained module placement and with minimized latency and area overheads. A test system will demonstrate a transfer rate of 800 MB/s while providing an extreme high placement flexibility. © 2008 IEEE.

Authors with CRIS profile

Christian Haubelt Technische Fakultät Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Related research project(s)

Design methodology for embedded system made upon small networks of hardware reconfigurable nodes and connections (ReCoNets) SPP 1148: Rekonfigurierbare Rechensysteme June 1, 2003 - May 31, 2009 Optimization methodologies for reconfiguration management on reconfigurable hardware nodes (ReCoNodes) SPP 1148: Rekonfigurierbare Rechensysteme June 1, 2003 - May 31, 2009

How to cite

APA:

Haubelt, C., Koch, D., & Teich, J. (2008). Efficient reconfigurable on-chip buses for fpgas. In Proceedings 16th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2008) (pp. 287-290). Palo Alto, California, US.

MLA:

Haubelt, Christian, Dirk Koch, and Jürgen Teich. "Efficient reconfigurable on-chip buses for fpgas." Proceedings of the 16th IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM'08, Palo Alto, California 2008. 287-290.

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