GSM900/DCS1800 Fractional-N Frequency Synthesizer with Very Fast Settling Time
Neurauter B, Märzinger G, Lüftner T, Weigel R, Scholz M, Mutlu V, Fenk J (2001)
Publication Type: Conference contribution
Publication year: 2001
Publisher: IEEE, MTT-S
Book Volume: 2
Pages Range: 705-708
Conference Proceedings Title: Microwave Symposium
Event location: Phoenix, USA
ISBN: 978-0-7803-6538-4
DOI: 10.1109/MWSYM.2001.966991
Abstract
This paper presents a programmable phase-locked-loop (PLL)-based fractional-N frequency synthesizer that uses a third-order ΔΣ-modulator. The in-band phase noise of -97 dBc/Hz in the integer-mode and -94 dBc/Hz in the fractional-mode is measured at 30 kHz offset. In addition to offering an ultra-fine frequency resolution of down to 12.4 Hz and very low in-band phase noise this frequency synthesizer offers, with a loop-bandwidth of about 100 kHz, a very fast settling time of less than 95 μs when a 75 MHz jump is applied. This feature enables multiple RF applications, including GSM to send a signal and quickly reset to send another signal to meet high data throughput requirements.
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Austria (AT)How to cite
APA:
Neurauter, B., Märzinger, G., Lüftner, T., Weigel, R., Scholz, M., Mutlu, V., & Fenk, J. (2001). GSM900/DCS1800 Fractional-N Frequency Synthesizer with Very Fast Settling Time. In Microwave Symposium (pp. 705-708). Phoenix, USA: IEEE, MTT-S.
MLA:
Neurauter, Burkhard, et al. "GSM900/DCS1800 Fractional-N Frequency Synthesizer with Very Fast Settling Time." Proceedings of the Microwave Symposium, Phoenix, USA IEEE, MTT-S, 2001. 705-708.
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