Automatic FIR Filter Generation for FPGAs

Dutta H, Hannig F, Teich J (2005)

Publication Type: Conference contribution

Publication year: 2005

Journal

Lecture Notes in Computer Science Springer Verlag

Publisher: Springer-verlag

Edited Volumes: Lecture Notes in Computer Science

Series: Lecture Notes in Computer Science (LNCS)

City/Town: Berlin, Heidelberg, New York

Book Volume: 3553

Pages Range: 51-61

Conference Proceedings Title: In Proceedings of the 5th International Workshop on Embedded Computer Systems, Architectures, Modeling, and Simulation (SAMOS 2005)

Event location: Island of Samos GR

ISBN: 3-540-26969-X

Abstract

This paper presents a new tool for the automatic generation of highly parallelized Finite Impulse Response (FIR) filters. In this approach we follow our PARO design methodology. PARO is a design system project for modeling, transformation, optimization, and synthesis of massively parallel VLSI architectures. The FIR filter generator employs during the design flow the following advanced transformations, (a) hierarchical partitioning in order to balance the amount of local memory with external communication, and (b), partial localization to achieve higher throughput and smaller latencies. Furthermore, our filter generator allows for design space exploration to tackle trade-offs in cost and speed. Finally, synthesizable VHDL code is generated and mapped to an FPGA, the results are compared with a commercial filter generator. © Springer-Verlag Berlin Heidelberg 2005.

Authors with CRIS profile

Hritam Dutta Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Frank Hannig Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Related research project(s)

Co-Design of Massively Parallel Embedded Processor Architectures (CoMap) Jan. 1, 2005 - Dec. 31, 2011 Dedizierte massiv parallele Systeme (PARO) Jan. 3, 2000 - Jan. 3, 2003

How to cite

APA:

Dutta, H., Hannig, F., & Teich, J. (2005). Automatic FIR Filter Generation for FPGAs. In In Proceedings of the 5th International Workshop on Embedded Computer Systems, Architectures, Modeling, and Simulation (SAMOS 2005) (pp. 51-61). Island of Samos, GR: Berlin, Heidelberg, New York: Springer-verlag.

MLA:

Dutta, Hritam, Frank Hannig, and Jürgen Teich. "Automatic FIR Filter Generation for FPGAs." Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation., Island of Samos Berlin, Heidelberg, New York: Springer-verlag, 2005. 51-61.

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