A 0.039 mm2 Inverter-Based 1.82 mW 68.6 dB-SNDR 10 MHz-BW CT-Sigma Delta-ADC in 65 nm CMOS Using Power- and Area-Efficient Design Techniques

Zeller S, Muenker C, Weigel R, Ußmüller T (2014)

Publication Type: Journal article

Publication year: 2014

Journal

IEEE Journal of Solid-State Circuits Institute of Electrical and Electronics Engineers (IEEE)

Book Volume: 49

Pages Range: 1548-1560

Journal Issue: 7

DOI: 10.1109/JSSC.2014.2321063

Authors with CRIS profile

Sebastian Zeller Lehrstuhl für Technische Elektronik Robert Weigel Lehrstuhl für Technische Elektronik Thomas Ußmüller Lehrstuhl für Technische Elektronik

How to cite

APA:

Zeller, S., Muenker, C., Weigel, R., & Ußmüller, T. (2014). A 0.039 mm2 Inverter-Based 1.82 mW 68.6 dB-SNDR 10 MHz-BW CT-Sigma Delta-ADC in 65 nm CMOS Using Power- and Area-Efficient Design Techniques. IEEE Journal of Solid-State Circuits, 49(7), 1548-1560. https://doi.org/10.1109/JSSC.2014.2321063

MLA:

Zeller, Sebastian, et al. "A 0.039 mm2 Inverter-Based 1.82 mW 68.6 dB-SNDR 10 MHz-BW CT-Sigma Delta-ADC in 65 nm CMOS Using Power- and Area-Efficient Design Techniques." IEEE Journal of Solid-State Circuits 49.7 (2014): 1548-1560.

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