Symbolic Multi-Level Loop Mapping of Loop Programs for Massively Parallel Processor Arrays

Tanase AP, Witterauf M, Teich J, Hannig F (2017)

Publication Type: Journal article, Original article

Publication year: 2017

Journal

ACM Transactions on Embedded Computing Systems Association for Computing Machinery (ACM)

Book Volume: 17

Pages Range: 31:1-31:27

Journal Issue: 2

DOI: 10.1145/3092952

Authors with CRIS profile

Alexandru-Petru Tanase Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Michael Witterauf Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Frank Hannig Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Related research project(s)

Compilation and Code Generation for Invasive Programs (C03) (TRR 89) DFG SFB/Transregio 89 "Invasive Computing" (TRR 89) July 1, 2010 - Dec. 31, 2022 Invasive Tightly-Coupled Processor Arrays (B02) (SFB/TRR 89 InvasIC (B02)) DFG SFB/Transregio 89 "Invasive Computing" (TRR 89) July 1, 2010 - Dec. 31, 2022 Dedizierte massiv parallele Systeme (PARO) Jan. 3, 2000 - Jan. 3, 2003

How to cite

APA:

Tanase, A.-P., Witterauf, M., Teich, J., & Hannig, F. (2017). Symbolic Multi-Level Loop Mapping of Loop Programs for Massively Parallel Processor Arrays. ACM Transactions on Embedded Computing Systems, 17(2), 31:1-31:27. https://doi.org/10.1145/3092952

MLA:

Tanase, Alexandru-Petru, et al. "Symbolic Multi-Level Loop Mapping of Loop Programs for Massively Parallel Processor Arrays." ACM Transactions on Embedded Computing Systems 17.2 (2017): 31:1-31:27.

BibTeX: Download