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Compilation Techniques for CGRAs: Exploring All Parallelization Approaches

Vander Aa T, Raghavan P, Mahlke S, De Sutter B, Shrivastava A, Hannig F (2010)

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Publication Type: Conference contribution

Publication year: 2010

Edited Volumes: Embedded Systems Week 2010 - Proceedings of the 8th IEEE/ACM/IFIP International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CODES+ISSS'2010

Pages Range: 185-186

Conference Proceedings Title: Proc. 8th International Conference on Hardware-Software Codesign and System Synthesis

Event location: Scottsdale, AZ

ISBN: 978-1-60558-902-2

DOI: 10.1145/1878961.1878995

Abstract

On behalf of the CODES+ISSS 2010 Program Committee, we would like to welcome you to the 8th IEEE/ACM International Conference on Hardware/Software- Co-Design and System Synthesis. CODES+ISSS is the premier conference for system-level design, with a focus on the design of embedded systems hardware, software, and tools. This year we continue the tradition of maintaining a high-quality forum for active discussion on current and innovative topics on embedded systems that bring together the latest in academic and industrial research and development. We selected the best submitted papers through a rigorous review process, and have assembled an exciting program with a mix of keynotes, tutorials, special sessions, and regular papers. This year we received 98 full paper submissions and selected 33 papers for publication, with an acceptance rate of 34%. The Program Committee carefully reviewed all papers, with an average of 4 reviews per paper. The Committee then met face to face for detailed discussions on the papers. Final paper selections were based on overall quality and novelty. Active interaction between presenters and audience has been traditionally extremely important in this conference. To encourage this we have organized poster sessions during the last 30 minutes of every session. This will give you the opportunity to discuss with all presenters independently of which of the two parallel tracks you attended. We trust you will find this year's program to be exciting and stimulating. It truly contains important advances in theory and practice of systemlevel design and related areas. We also continue the tradition of complementing the CODES+ISSS program with tutorials and special sessions. This year's tutorials and special sessions cover timely and emerging topics such as the future of interconnect; best practices and new directions for system level design; challenges and opportunities in high performance computing; an introduction to the new standard for SystemC synthesis; and compilation techniques for coarse-grain programmable arrays. CODES+ISSS is part of the growing Embedded Systems Week (ESWEEK) event that is becoming the premier international event in embedded systems research and development. CODES+ISSS is complemented by two other flagship sister conferences: EMSOFT, and CASES. Registrants to ESWEEK may attend sessions in any of the three conferences. The technical programs of the three conferences, including keynotes, special sessions, panels, tutorials and workshops, have been carefully planned to avoid major overlaps and complement each other.

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How to cite

APA:

Vander Aa, T., Raghavan, P., Mahlke, S., De Sutter, B., Shrivastava, A., & Hannig, F. (2010). Compilation Techniques for CGRAs: Exploring All Parallelization Approaches. In Proc. 8th International Conference on Hardware-Software Codesign and System Synthesis (pp. 185-186). Scottsdale, AZ, US.

MLA:

Vander Aa, Tom, et al. "Compilation Techniques for CGRAs: Exploring All Parallelization Approaches." Proceedings of the International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS'10), Scottsdale, AZ 2010. 185-186.

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