A Rapid Prototyping System for Error-Resilient Multi-Processor Systems-on-Chip

May M, Wehn N, Bouajila A, Zeppenfeld J, Stechele W, Herkersdorf A, Ziener D, Teich J (2010)

Publication Type: Conference contribution

Publication year: 2010

Edited Volumes: Proceedings -Design, Automation and Test in Europe, DATE

Pages Range: 375-380

Conference Proceedings Title: Proc. Design, Automation and Test in Europe

Event location: Dresden DE

ISBN: 978-1-4244-7054-9

Abstract

Static and dynamic variations, which have negative impact on the reliability of microelectronic systems, increase with smaller CMOS technology. Thus, further downscaling is only profitable if the costs in terms of area, energy and delay for reliability keep within limits. Therefore, the traditional worst case design methodology will become infeasible. Future architectures have to be error resilient, i.e., the hardware architecture has to tolerate autonomously transient errors. In this paper, we present an FPGA based rapid prototyping system for multi-processor systems-on-chip composed of autonomous hardware units for error-resilient processing and interconnect. This platform allows the fast architectural exploration of various error protection techniques under different failure rates on the microarchitectural level while keeping track of the system behavior. We demonstrate its applicability on a concrete wireless communication system. © 2010 EDAA.

Authors with CRIS profile

Daniel Ziener Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Involved external institutions

Technische Universität Kaiserslautern DE Germany (DE) Technische Universität München (TUM) DE Germany (DE)

How to cite

APA:

May, M., Wehn, N., Bouajila, A., Zeppenfeld, J., Stechele, W., Herkersdorf, A.,... Teich, J. (2010). A Rapid Prototyping System for Error-Resilient Multi-Processor Systems-on-Chip. In Proc. Design, Automation and Test in Europe (pp. 375-380). Dresden, DE.

MLA:

May, Matthias, et al. "A Rapid Prototyping System for Error-Resilient Multi-Processor Systems-on-Chip." Proceedings of the Design, Automation and Test in Europe (DATE'10), Dresden 2010. 375-380.

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