A Reconfigurable Memory Architecture for System Integration of Coarse-Grained Reconfigurable Arrays

Sousa É, Tanase AP, Hannig F, Teich J (2017)

Publication Type: Conference contribution

Publication year: 2017

Event location: Cancun, Mexico MX

URI: http://ieeexplore.ieee.org/document/8279768/

DOI: 10.1109/RECONFIG.2017.8279768

Open Access Link: http://ieeexplore.ieee.org/document/8279768/

Authors with CRIS profile

Ericles Rodrigues Sousa Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Alexandru-Petru Tanase Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Frank Hannig Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Related research project(s)

Invasive Tightly-Coupled Processor Arrays (B02) (SFB/TRR 89 InvasIC (B02)) DFG SFB/Transregio 89 "Invasive Computing" (TRR 89) July 1, 2010 - Dec. 31, 2022 DFG SFB/Transregio 89 "Invasive Computing" (TRR 89) July 1, 2010 - Dec. 31, 2022 Integration and Coupling of Tightly Coupled Processor Arrays (T01) (TCPA_INT) DFG SFB/Transregio 89 "Invasive Computing" (TRR 89) March 1, 2017 - Feb. 29, 2020

How to cite

APA:

Sousa, É., Tanase, A.-P., Hannig, F., & Teich, J. (2017). A Reconfigurable Memory Architecture for System Integration of Coarse-Grained Reconfigurable Arrays. In Proceedings of the International Conference on ReConFigurable Computing and FPGA's (ReConFig). Cancun, Mexico, MX.

MLA:

Sousa, Éricles, et al. "A Reconfigurable Memory Architecture for System Integration of Coarse-Grained Reconfigurable Arrays." Proceedings of the International Conference on ReConFigurable Computing and FPGA's (ReConFig), Cancun, Mexico 2017.

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