FPGA designs of parallel high performance GF(2^233) multipliers

Grabbe C, Bednara M, Teich J, von zur Gathen J, J. Shokrollahi J (2003)

Publication Status: Published

Publication Type: Conference contribution, Conference Contribution

Publication year: 2003

Book Volume: 2

Pages Range: 268-271

Conference Proceedings Title: Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS-2003)

Event location: Bangkok TH

URI: https://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=0038790049&origin=inward

Abstract

For many applications from the areas of cryptography and coding, finite field multiplication is the most resource and time consuming operation. We have designed and optimized four high performance parallel GF(2) multipliers for an FPGA realization and analyzed the time and area complexities. One of the multipliers uses a new hybrid structure to implement the Karatsuba algorithm. For increasing performance, we make excessive use of pipelining and efficient control techniques and use a modern state-of-the-art FPGA technology. As a result we have, to our knowledge, the first hardware realization of subquadratic arithmetic and currently the fastest and most efficient implementation of 233 bit finite field multipliers.

Authors with CRIS profile

Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Involved external institutions

Universität Paderborn DE Germany (DE)

How to cite

APA:

Grabbe, C., Bednara, M., Teich, J., von zur Gathen, J., & J. Shokrollahi, J. (2003). FPGA designs of parallel high performance GF(2^233) multipliers. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS-2003) (pp. 268-271). Bangkok, TH.

MLA:

Grabbe, Cornelia, et al. "FPGA designs of parallel high performance GF(2^233) multipliers." Proceedings of the Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, Bangkok 2003. 268-271.

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