Dynamic Reconfiguration of Distributed Arithmetic Controllers: Design Space Exploration and Trade-off Analysis
Bobda C, Danne K (2004)
Publication Type: Conference contribution
Publication year: 2004
Edited Volumes: Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2004 (Abstracts and CD-ROM)
Conference Proceedings Title: Proc. Reconfigurable Architecture Workshop 2004
Event location: Santa Fé NM
ISBN: 0-7695-2132-0
Abstract
This work explores various solutions to implement an application using runtime reconfigurable field programmable gate arrays (FPGA). The example is a mechatronic control system which has to adapt its behavior from time to time. Our model is a task-graph where every task is associated with an hardware module characterized by its required FPGA resource and its execution time. We propose various mappings of the tasks onto the FPGA. For the implementation of the tasks themselves the computation technique known as distributed arithmetic is used. We achieve numerous alternatives with different resource consumptions and execution times for every task. We estimate these characteristics and compare them to synthesis results. The received values are used to get the characteristics of the over-all system. The results show that the optimal mapping depends on the application timing constrains, on the complexity of the tasks as well as on the reconfiguration speed of the used FPGA1.
Involved external institutions
Germany (DE)How to cite
APA:
Bobda, C., & Danne, K. (2004). Dynamic Reconfiguration of Distributed Arithmetic Controllers: Design Space Exploration and Trade-off Analysis. In Proc. Reconfigurable Architecture Workshop 2004. Santa Fé NM.
MLA:
Bobda, Christophe, and Klaus Danne. "Dynamic Reconfiguration of Distributed Arithmetic Controllers: Design Space Exploration and Trade-off Analysis." Proceedings of the Reconfigurable Architecture Workshop 2004, Santa Fé NM 2004.
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