Optimal FPGA Module Placement with Temporal Precedence Constraints

Fekete SP, Köhler E, Teich J (2001)

Publication Type: Conference contribution

Publication year: 2001

Edited Volumes: Proceedings -Design, Automation and Test in Europe, DATE

Pages Range: 658-665

Conference Proceedings Title: Proc. DATE 2001, Design, Automation and Test in Europe

Event location: Munich DE

DOI: 10.1109/DATE.2001.915093

Abstract

We consider the optimal placement of hardware modules in space and time for FPGA architectures with reconfiguration capabilities, where modules are modeled as three-dimensional boxes in space and time. Using a graph-theoretic characterization of feasible packings, we are able to solve the following problems. (a) Find the minimal execution time of the given problem on an FPGA of fixed size, (b) Find the FPGA of minimal size to accomplish the tasks within a fired time limit. Furthermore, our approach is perfectly suited for the treatment of precedence constraints for the sequence of tasks, which are present in virtually all practical instances. Additional mathematical structures are developed that lead to a powerful framework for completing optimal solutions. The usefulness is illustrated by computational results. © 2001 IEEE.

Authors with CRIS profile

Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Involved external institutions

Technische Universität Braunschweig DE Germany (DE) Technische Universität Berlin DE Germany (DE)

How to cite

APA:

Fekete, S.P., Köhler, E., & Teich, J. (2001). Optimal FPGA Module Placement with Temporal Precedence Constraints. In Proc. DATE 2001, Design, Automation and Test in Europe (pp. 658-665). Munich, DE.

MLA:

Fekete, Sandor P., Ekkehard Köhler, and Jürgen Teich. "Optimal FPGA Module Placement with Temporal Precedence Constraints." Proceedings of the DATE 2001, Design, Automation and Test in Europe,, Munich 2001. 658-665.

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