EXPLORA - Generic Design Space Exploration During Embedded System Synthesis

Cieslok F, Esau H, Teich J (2000)

Publication Type: Conference contribution

Publication year: 2000

Pages Range: 215-225

Conference Proceedings Title: Proc. DIPES 2000, Int. IFIP Workshop on Distributed and Parallel Embedded Systems

Event location: Schloss Eringerfeld DE

Authors with CRIS profile

Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Related research project(s)

Dedizierte massiv parallele Systeme (PARO) Jan. 3, 2000 - Jan. 3, 2003

Involved external institutions

Universität Paderborn DE Germany (DE)

How to cite

APA:

Cieslok, F., Esau, H., & Teich, J. (2000). EXPLORA - Generic Design Space Exploration During Embedded System Synthesis. In Proc. DIPES 2000, Int. IFIP Workshop on Distributed and Parallel Embedded Systems (pp. 215-225). Schloss Eringerfeld, DE.

MLA:

Cieslok, Frank, Heinrich Esau, and Jürgen Teich. "EXPLORA - Generic Design Space Exploration During Embedded System Synthesis." Proceedings of the Int. IFIP Workshop on Distributed and Parallel Embedded Systems,, Schloss Eringerfeld 2000. 215-225.

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