A Compact Analog Active Time delay Line using SiGe BiCMOS Technology

Hamouda M, Fischer G, Weigel R, Ußmüller T (2013)

Publication Type: Conference contribution

Publication year: 2013

Conference Proceedings Title: IEEE International Symposium on Circuits and Systems

Event location: Beijing

DOI: 10.1109/ISCAS.2013.6572031

Abstract

This work discusses the design of a 60ps delay element for UWB analog signals ranging from 0.05 up to 7.5GHz. The design is implemented using BJT transistors which have the advantage of being very compact in area compared to the passive architectures. The proposed architecture is flexible and can be cascaded to have delay upto 210ps with 3dB insertion loss. The circuit is designed using low cost 0.25μm 95GHz fmax SiGe-HBTBiCMOS process technology consuming a power of 121mW. The estimated consumed area of the circuit is 560μm x 870μm.

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How to cite

APA:

Hamouda, M., Fischer, G., Weigel, R., & Ußmüller, T. (2013). A Compact Analog Active Time delay Line using SiGe BiCMOS Technology. In IEEE International Symposium on Circuits and Systems. Beijing, CN.

MLA:

Hamouda, Mohammed, et al. "A Compact Analog Active Time delay Line using SiGe BiCMOS Technology." Proceedings of the IEEE International Symposium on Circuits and Systems, Beijing 2013.

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