Dürbaum T (2004)
Publication Type: Conference contribution, Conference Contribution
Publication year: 2004
Edited Volumes: Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC
Pages Range: Paper D7.11
Conference Proceedings Title: Proceedings APEC 2004
Event location: Anaheim, California,
ISBN: 07803-8270-6 (CD-ROM)
This paper presents a time domain measurement method to estimate the parasitic inductance of a Printed Circuit Board (PCB) layout. It is based on a lumped element model. The proposed measurement technique is also used for measuring the Equivalent Series Inductance (ESL) of devices such as low ohmic MOSFETs and high current shunt resistors. The PCB layout of a half bridge circuit is characterised as an application example.
APA:
Dürbaum, T. (2004). PCB Layout Inductance Modeling Based on a Time Domain Measurement Approach. In Proceedings APEC 2004 (pp. Paper D7.11). Anaheim, California,.
MLA:
Dürbaum, Thomas. "PCB Layout Inductance Modeling Based on a Time Domain Measurement Approach." Proceedings of the APEC 2004 - Nineteenth Annual IEEE Applied Power Electronics Conference and Exhibition, Anaheim, California, 2004. Paper D7.11.
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