A 1.8-mW Low Power, PVT-Resilient, High Linearity, modified Gilbert-Cell Down-Conversion Mixer in 28-nm CMOS

Ciocoveanu R, Rimmelspacher J, Weigel R, Hagelauer AM, Issakov V (2018)


Publication Language: English

Publication Status: Accepted

Publication Type: Conference contribution, Conference Contribution

Future Publication Type: Conference contribution

Publication year: 2018

Pages Range: 19-22

Event location: Anaheim, USA

DOI: 10.1109/SIRF.2018.8304218

Abstract

This paper presents a high linearity modified Gilbert-cell mixer designed for 60-GHz applications and fabricated in a 28-nm CMOS technology. To increase the linearity of the mixer, the RF transconductance stage was removed, thereby reducing the amount of stacked transistors. We propose using a self-biasing Vth reference in the bias network to make the mixer more robust to process-voltagetemperature (PVT) variations. Measurement results show that this mixer achieves a voltage conversion gain of 4.7 dB, a 1-dB compression point of -3 dBm and a 12.3 dB noise figure, while it draws only 2 mA from a single 0.9 V supply. The occupied area on the chip is 0.35x0.68 mm2 including pads.

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How to cite

APA:

Ciocoveanu, R., Rimmelspacher, J., Weigel, R., Hagelauer, A.M., & Issakov, V. (2018). A 1.8-mW Low Power, PVT-Resilient, High Linearity, modified Gilbert-Cell Down-Conversion Mixer in 28-nm CMOS. In Proceedings of the Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (pp. 19-22). Anaheim, USA.

MLA:

Ciocoveanu, Radu, et al. "A 1.8-mW Low Power, PVT-Resilient, High Linearity, modified Gilbert-Cell Down-Conversion Mixer in 28-nm CMOS." Proceedings of the Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, Anaheim, USA 2018. 19-22.

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