Loop Coarsening in C-based High-Level Synthesis

Schmid M, Reiche O, Hannig F, Teich J (2015)

Publication Language: English

Publication Type: Conference contribution, Conference Contribution

Publication year: 2015

Publisher: IEEE

Pages Range: 166-173

Conference Proceedings Title: Proceedings of the 26th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)

Event location: Toronto CA

ISBN: 978-1-4799-1925-3

URI: https://www12.cs.fau.de/downloads/reiche/publications/SRHT15.pdf

DOI: 10.1109/ASAP.2015.7245730

Abstract

Current tools for High-Level Synthesis (HLS) excel at exploiting Instruction-Level Parallelism (ILP), the support for Data-Level Parallelism (DLP), one of the key advantages of Field Programmable Gate Arrays (FPGAs), is in contrast very limited. This work examines the exploitation of DLP on FPGAs using code generation for C-based HLS of image filters and streaming pipelines, consisting of point and local operators. In addition to well known loop tiling techniques, we propose loop coarsening, which delivers superior performance and scalability. Loop tiling corresponds to splitting an image into separate regions, which are then processed in parallel by replicated accelerators. For data streaming, this also requires the generation of glue logic for the distribution of image data. Conversely, loop coarsening allows to process multiple pixels in parallel, whereby only the kernel operator is replicated within a single accelerator. We augment the FPGA back end of the heterogeneous Domain-Specific Language (DSL) framework HIPAcc by loop coarsening and compare the resulting FPGA accelerators to highly optimized software implementations for Graphics Processing Units (GPUs), all generated from the exact same code base. Moreover, we demonstrate the advantages of code generation for algorithm development by outlining how design space exploration enabled by HIPAcc can yield a more efficient implementation than handcoded VHDL.

Authors with CRIS profile

Moritz Schmid Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Oliver Reiche Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Frank Hannig Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Related research project(s)

GRK 1773: Heterogeneous Image Systems, Project B3 (GRK 1773) RTG 1773: Heterogeneous Image Systems Oct. 1, 2012 - March 31, 2017

How to cite

APA:

Schmid, M., Reiche, O., Hannig, F., & Teich, J. (2015). Loop Coarsening in C-based High-Level Synthesis. In Proceedings of the 26th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) (pp. 166-173). Toronto, CA: IEEE.

MLA:

Schmid, Moritz, et al. "Loop Coarsening in C-based High-Level Synthesis." Proceedings of the 26th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Toronto IEEE, 2015. 166-173.

BibTeX: Download