Representing mapping and scheduling decisions within dataflow graphs

Zebelein C, Haubelt C, Falk J, Schwarzer T, Teich J (2013)

Publication Status: Published

Publication Type: Conference contribution, Conference Contribution

Publication year: 2013

Pages Range: 8

Article Number: 6646654

Conference Proceedings Title: Proceedings of Forum on Specification & Design Languages (FDL 2013)

Event location: Paris FR

ISBN: 9782953050486

URI: https://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=84891286674&origin=inward

Abstract

Choosing the right programming model for multiprocessor System-on-Chip (MPSoC) platforms is a challenging task: in order to provide for automatic hardware/software synthesis in a model-based design flow, the system model should be architecture-independent on the one hand, but should also allow the back-annotation of architecture-dependent mapping and scheduling decisions on the other hand. Here, architecture-independent dataflow models are particularly suitable. In a dataflow model, concurrent processes (actors) communicate via packets transmitted over channels. However, the back-annotation process is difficult, and previous approaches are either restricted to static dataflow actors or static schedules. Also, the semantics of the underlying dataflow actors are often different from the semantics of the scheduling mechanism, which limits the compositionality of the dataflow model. In this paper, we propose a modeling approach which unifies the representation of dataflow actors and scheduling mechanisms, while also providing for both, dynamic dataflow actors and dynamic scheduling decisions. We describe how various scheduling schemes can be represented by our approach, and show the applicability of the proposed approach by means of synthetic dataflow graphs. © 2013 European Electronic Chips & Systems design Initiative - ECSI.

Authors with CRIS profile

Joachim Falk Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Tobias Schwarzer Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Related research project(s)

Actor-Oriented Synthesis and Optimization of Digital Hardware/Software Systems at System-Level (AEOS) March 1, 2010 - Dec. 31, 2015

Involved external institutions

Universität Rostock DE Germany (DE)

How to cite

APA:

Zebelein, C., Haubelt, C., Falk, J., Schwarzer, T., & Teich, J. (2013). Representing mapping and scheduling decisions within dataflow graphs. In Proceedings of Forum on Specification & Design Languages (FDL 2013) (pp. 8). Paris, FR.

MLA:

Zebelein, Christian, et al. "Representing mapping and scheduling decisions within dataflow graphs." Proceedings of the 2013 16th Forum on Specification and Design Languages, FDL 2013, Paris 2013. 8.

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