Reconfigurable Hardware Generation of Multigrid Solvers with Conjugate Gradient Coarse-Grid Solution
Schmitt C, Schmid M, Kuckuk S, Köstler H, Teich J, Hannig F (2018)
Publication Status: Published
Publication Type: Journal article, Original article
Future Publication Type: Journal article
Publication year: 2018
Journal
Publisher: World Scientific
Edited Volumes: Parallel Processing Letters
Book Volume: 28
Article Number: 1850016
Journal Issue: 4
DOI: 10.1142/S0129626418500160
Abstract
Not only in the field of high-performance computing, field-programmable gate arrays (FPGAs) are a soaringly popular accelerator technology. However, they use a completely different programming paradigm and tool set compared to CPUs or even GPUs, adding extra development steps and requiring special knowledge, hindering widespread use in scientific computing. To bridge this programmability gap, domain-specific languages are a popular choice to generate low-level implementations from an abstract algorithm description. In this work, we demonstrate our approach for the generation of numerical solver implementations based on the multigrid method for FPGAs from the same code base that is also used to generate code for CPUs using a hybrid parallelization of MPI and OpenMP. Our approach yields in a hardware design that can compute up to 11 V-cycles per second with an input grid size of 4096x4096 and solution on the coarsest using the conjugate gradient method on a mid-range FPGA, beating vectorized, multi-threaded execution on an Intel Xeon processor.
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APA:
Schmitt, C., Schmid, M., Kuckuk, S., Köstler, H., Teich, J., & Hannig, F. (2018). Reconfigurable Hardware Generation of Multigrid Solvers with Conjugate Gradient Coarse-Grid Solution. Parallel Processing Letters, 28(4). https://doi.org/10.1142/S0129626418500160
MLA:
Schmitt, Christian, et al. "Reconfigurable Hardware Generation of Multigrid Solvers with Conjugate Gradient Coarse-Grid Solution." Parallel Processing Letters 28.4 (2018).
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